Circuit/device modeling at the quantum level

Quantum mechanical (QM) effects, which manifest when the device dimensions are comparable to the de Broglie wavelength, are becoming common physical phenomena in the current micro-/nano-meter technology era. While most novel devices take advantage of QM effects to achieve fast switching speed, miniature size, and extremely small power consumption, the mainstream CMOS devices (with the exception of EEPROMs) are generally suffering in performance from these effects. Solutions to minimize the adverse effects caused by QM while keeping the downscaling trend (technology feasibility aside) are being sought in the research community and industry-wide. This paper presents a perspective view of modeling approaches to quantum mechanical effects in solid-state devices at the device and circuit simulation levels. Specifically, the macroscopic modeling of silicon devices to include QM corrections in the classical transport framework is discussed. Both device and circuit models will be provided. On the quantum devices, such as the single electron junctions and transistors, the emphasis is placed on the principle of logic circuit operation.