An efficient statistical model using electrical tests for GHz CMOS devices

A practical statistical SPICE model has been developed for computer-aided design of high performance devices. This model accounts for both interdie and intra-die device variations, both of which contribute to statistical variations in chip performance. A new characterization method, ET-based SPICE modeling, is proposed in order to link the shift of E-tests (Electrical tests) to the SPICE input deck without additional measurements of I-V curves. Therefore, we can efficiently analyze the chip performance with respect to the process variations. The model is applied to a 2.0 V 1.6 GHz bandwidth DRAM which has 0.19 /spl mu/m triple-well, 4-poly, 2-metal CMOS process. The simulated chip performance variability agrees well with measured data.