RNS arithmetic multiplier for medium and large moduli

In implementing Residue Number System (RNS) arithmetic multipliers, ROM-based structures are very efficient for small moduli, However, due to their exponential growth, ROM implementations are not suitable for medium and large moduli. This paper introduces an architecture for a RNS-based multiplier which combines the use of small-size ROMs and arithmetic components. The design is most suitable for medium and large moduli. Compared with other implementations, the VLSI layout implementation of this new approach is shown to be more efficient in terms of area and delay requirements.