TCAD diagnosis of I/O-pin latchup in scaled-DRAM

Summary form only given. This paper describes a TCAD analysis of I/O-pin latchup failure found in a shallow-well CMOS DRAM. The 0.35 /spl mu/m DRAM I/O-pin showed significant degradation in latchup test of JEDEC Standard over-current stress. TCAD diagnosis of the failure was conducted and newly clarified the biasing effect of the guard-band (N/sup +/) layer and the layout-related latchup mechanism, which leads to a practical latchup-immunity design in sub-/spl mu/m CMOS process and layout. To overcome process-margin problem against latchup, a simple CMOS process is proposed for the 0.35 /spl mu/m DRAM.