Study of the extended p/sup +/ dual source structure for eliminating bipolar induced breakdown in submicron SOI MOSFET's

Simulation results on a novel extended p/sup +/ dual source SOI MOSFET are reported. It is shown that the presence of the extended p/sup +/ region on the source side, which can he fabricated using post-low-energy implanting selective epitaxy (PLISE), significantly suppresses the parasitic bipolar transistor action resulting in a large improvement in the breakdown voltage. Our results show that when the length of the extended p/sup +/ region is half the channel length, the improvement in breakdown voltage is about 120% when compared to the conventional SOI MOSFET's.