A highly linear low-power 10 bit DAC for GSM

A 10-bit 6.5 MS/s DAC designed for a GSM baseband transmit channel is described. It features a low power quasipassive architecture with segmentation and element mismatch-shaping used in the conversion of the four MSBs. The DAC charge is entered into an integrated switched-capacitor biquad filter with passive charge sharing in the output stage, which passes the signal to a continuous time output stage. The DAC achieves less than 1/4 bit DNL and 0.6 bit INL at the 10-bit level with no calibration or trimming.