A dielectric-defined process for the formation of T-gate field-effect transistors

A novel process for the fabrication of tee- or gamma-shaped gate structures is presented. This process was utilized to fabricate 0.25 mu m*60 mu m and 0.25 mu m*150 mu m T-gate MESFETs. From S-parameter data up to 40 GHz, extrapolated cutoff frequencies as high as 55-65 GHz were obtained. DC yields as high as 80% over 3-in wafers were obtained using this dielectric defined T-gate (DDTG) process. Step-stress measurements indicate device reliability comparable to the normal MESFET process. Relative to multilayer resist processing techniques usually used to form T-gates, it is believed that the DDTG process will substantially increase the yield, uniformity, and reliability of FET-like devices/circuits using T-gates with geometries at or below 0.25 mu m.<
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