Cache coherence protocol verification of a multiprocessor system with shared memory

In this paper, we present the verification of a multiprocessor system with shared memory, using VIS tool. This system consists of three processors; each one has its cache and all share the main memory and the bus. Its RTL-level design is described in Verilog-HDL and the properties to be verified, in CTL. Also, we establish the effect of data width upon the reachability analysis. As results, safety and liveness properties are fulfilled by the system design, and a fast increase of reachable state number and BDD (Binary Decision Diagram) size is observed when the data width or the processor number are growing. By using MDG tool, we plan to resolve the negative effect of cache size increase.