High performance transistors with state-of-the-art CMOS technologies

High performance 90 nm CMOS transistors have been developed using channel epitaxy, poly Si/sub 1-x/Ge/sub x/ gate, elevated source/drain (S/D), and nickel salicide (NiSi) technologies with boron-penetration-free 20 /spl Aring/ gate dielectric. For the first time, these novel technologies are employed all together, and, merits and demerits are characterized in the high performance limit. For NMOS, I/sub dsat/(saturation-current)=890 /spl mu/A//spl mu/m at V/sub dd/=1.5 V, I/sub doff/(off-current)=1 nA//spl mu/m with improved linear and saturation transconductances has been achieved using channel epitaxy. For NMOS, I/sub dsat/=355 /spl mu/A//spl mu/m has been achieved using NiSi with significantly reduced junction leakage and gate R/sub s/. The junction capacitance has been reduced by 40% using elevated S/D, while the level of gate poly depletion has been reduced using poly Si/sub 1-x/Ge/sub x/ gate. Especially, a PMOS transistor using all novel technologies has been fabricated with L/sub gate/(gate-length)=145 nm for better manufacturability. This device has exhibited all superior characteristics described above at the same time, as a result, the PMOS gate delay is estimated to be reduced by 21%. It is important to note that this device is apt for the volume production of high-speed logic LSIs.