A simulation-based analog cell synthesis with improved simulation efficiency

This paper presents a new simulation-based analog cell synthesis approach with improved simulation efficiency. For the hierarchical synthesis of analog cells we developed the sub-circuit optimizers such as current mirror and differential input stage. Each sub-circuit optimizer can be used for synthesis of analog cells such as OTA (operational transconductance amplifier), 2-stage op amp and comparator. To reduce the time spent on the simulation-based synthesis we propose a 2-stage searching scheme and simulation data reusing scheme. With those schemes the synthesis time spent for OTA was reduced from 301.05 sec to 56.52 sec or by 81.1%. Since our synthesis system doesn't need other additional physical parameters except SPICE parameters, and is independent of the process and its model level the time spent to port to other processes is minimized. We synthesized an OTA and 2-stage op amp respectively with our approach to show its usefulness.