Layout and Interconnect Optimization for Low-Power and High-Sensitivity Operation of $E$ -Band SiGe HBT Frequency Dividers

A layout and interconnect optimization techniques for low-power and high-sensitivity performance of static frequency dividers in E-band is reported. The layout optimization provides optimal transistor placement and identifies critical interconnects, which allows to reduce their parasitics. These measures provide high operation frequency and good sensitivity of the divider without a need of investing additional dc current.