Multi-channel multi-point distribution service system transceiver implementation

This paper presents the hardware implementation of a high-speed transceiver to be used in a multi-channel multi-point distribution system (MMDS). Based on standards specifications, various building blocks are implemented using FPGA prototypes. It has been found that data integrity protection is expensive to implement, namely the forward error correction scheme in the transceiver. This includes Reed-Solomon codec and byte interleaving to correct both random and burst errors causing by the channel. Results show a data rate of 80 Mbit/s can be achieved using FPGA prototypes. Higher data rates are expected when final ASICs are developed.