Retractile clock-powered logic

Retractile clock-powered logic is presented as a low-overhead energy-recovery logic style. It uses energy-efficient clock-steering circuits, pass-transistor logic, and a four-phase clocking scheme to recover energy from all circuit nodes but the latches. A 16-bit retractile clock-powered adder is described and evaluated through HSPICE simulations. The simulation results indicate that this approach can offer superior energy vs. delay performance but the benefit depends strongly on the switching activity of the clock-powered nodes.