Enabling shallow trench isolation for 0.1 /spl mu/m technologies and beyond

Shallow trench isolation (STI) has become the standard isolation structure for sub-micron silicon CMOS technologies (Perera et al, 1995; Chatterjee et al, 1996). However, following the trend of device scaling, isolation for future device generations will have minimum width of about 130 nm for 0.1 /spl mu/m technologies and 100 nm for 0.07 /spl mu/m technologies. It is highly desirable to extend the current STI structure (Nandakumar et al., 1998), widely adapted in manufacturing, to those dimensions, but many issues become difficult to resolve. In this work, we show that with a novel enabler, high temperature re-oxidation (HTR), for corner rounding (Chang et al., 1997) and by properly addressing the issues of trench fill, corner profiles, tub implants, channel width loss, reverse narrow channel effect (RNCE), defect density and junction leakage, the basic STI structure can be extended to 0.1 /spl mu/m and beyond.