New embedded DRAM technology using self-aligned salicide block (SSB) process for 0.18 /spl mu/m SOC (system on a chip)

New embedded DRAM technology for 0.18 /spl mu/m SOC (system on a chip) using the self-aligned salicide block (SSB) process is proposed. This process technology provides full process compatibility with high performance logic and minimum number of process steps, resulting in low process cost and short TAT (turnaround time). We fabricated a DRAM array macro using this technology with Co salicide, dual work function gate and aluminum bitline processes, and confirmed excellent DRAM retention characteristics by using a negative wordline bias scheme.