STI TEOS densification for furnaces and RTP tools

The traditional oxide densification anneal used to reduce the etch rate of TEOS relative to thermal oxide is inadequate for high-aspect ratio shallow trench isolation processes. Excessive removal of TEOS during wet oxide etches causes yield detractors such as seams (resulting in gate-to-gate shorts), divots (increasing corner leakage), and global TEOS pulldown (creating unwanted topography). Therefore, an alternative densification process was developed. In addition to the defect and device issues, there was incentive to develop a rapid thermal process (RTP) to reduce cycle time. This paper summarizes our work to improve the TEOS anneal process. The etch rate work on monitor wafers compares densification under furnace and RTP conditions for several different ambients and temperatures. The influence of wafer location in the furnace and of film variations through depth is also evaluated. Additionally, after an effective anneal process was extracted from the initial monitor work, it was implemented on 0.25 /spl mu/m CMOS and DRAM technologies in manufacturing. Electrical and physical data were used to evaluate the effectiveness of the anneal.