Analysis and optimization of a uniform long wire and driver

An analytical delay model of a uniform wire and driver, based on a combination of a switch-level model and Elmore delay is developed for the on-chip interconnections. The model is utilized for the optimization of delay, power, area, or combinations thereof, subject to different constraints. A linear relation between wire width and transistor widths is proposed, which leads to closed-form solutions to the optimization problems. These solutions are valid also for a multistage uniform wire and driver and are easily used in practical design. The solutions are compared to SPICE simulated results, using practical process parameters. Results show that the root of mean square (rms) errors of delay and power between SPICE simulation and the proposed method are around 3%.