Reconfigurable, conditional pre-charge SRAM: Lowering read power by leveraging data statistics

This paper presents a data-dependent SRAM paired with statistical methods to leverage data correlation for the purpose of low power read operations. A 10T bit-cell, a prediction-based conditional pre-charge circuit, and a compact column circuit implemented in a 16kbit 28nm SRAM test chip demonstrate power savings up to 69% for applications spanning signal processing, video coding and computer vision as compared to similar memories with naive prediction.