Synchronous-mode evaluation of delays in CMOS structures

The extension of the explicit formulation of delays in CMOS VLSI to synchronous-mode evaluation allows the accurate evaluation of data path timing (few percent with respect to SPICE simulation) of general CMOS structures for all available input drive configurations, resulting in fast identification of timing problems. A validation of this method has been done using general series parallel networks. It was shown to be sufficiently accurate for resolving race problems. An implementation of the proposed algorithms has been conceived as a preprocessor for an event-driven switch simulator and it has been shown to be fast enough for use in VLSI timing analysis.<
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