Impact of Interface Trap Charges on Performance of Electrically Doped Tunnel FET With Heterogeneous Gate Dielectric

In this paper, we investigate for the first time effect of positive (donor) and negative (acceptor) interface trap charges on the performance of proposed heterogeneous gate dielectric (HD) electrically doped tunnel field-effect transistor (EDTFET) in terms of dc, analog/RF, and linearity distortion parameters, where the HD layer is considered as a gate dielectric to improve the ON-state current and device performance. For this, a comparative analysis has been performed between conventional and proposed EDTFET with identical dimensions in the presence of interface trap charges. ATLAS device simulation of both devices is performed for different performance metrics such as transfer characteristics, parasitic capacitances, device efficiency, output conductance (gds), cut-off frequency (ft), and gain bandwidth product. However, linearity distortion parameters of the proposed device such as third-order transconductance coefficient (gm3), VIP2, VIP3, IIP3, and IMD3 are also investigated. The device simulations show that HD-EDTFET is more immune in terms of performance variation than conventional EDTFET with different interface trap charges available at the Si/SiO2 interface. Thus, it can be utilized as a suitable candidate for low power analog/RF applications.