A Low Power Inductorless Wideband LNA With Gm Enhancement and Noise Cancellation

This letter presents the design of an inductorless low power differential low-noise amplifier (LNA) in 65 nm Low Power (LP) CMOS technology for multi-standard radio applications between 100MHz and 4.3 GHz. Based on the combination of common-gate (CG) and common-source (CS) with shunt feedback (SFB) topologies, the LNA utilizes a cross-coupled push-pull structure to realize g
_m
boosting and partial noise cancelling under low power consumption. A cascode transistor is used to alleviate the Miller effect and also constructs a current steering structure to increase the bandwidth and gain. These techniques result in a good overall performance tradeoff after sizing and biasing optimization under the power constraint. A prototype has been implemented and it exhibits a voltage gain of 21.2 dB, an NF of 2.8-4 dB over the frequency range of 100 MHz to 4.3 GHz. It consumes 2 mW from 1.2 V supply and occupies an active area of 0.05 mm
²
.