Clock verification in the presence of IR-drop in the power distribution network

Clock nets are the most important circuits in high-speed digital systems. The design of clock circuitry and the quality of the clock signal directly impacts the performance of a VLSI chip. Clock verification requires high accuracy and is typically performed using circuit simulators. In high-performance deep-submicron digital circuits, clocks are running at higher frequencies and are driving more gates than ever, thus presenting a higher load on the power distribution network with the potential of substantial IR-drop. However, as IR-drop is a full-chip phenomenon, circuit simulation is extremely time consuming. In this paper, we present a loosely coupled iterative technique for clock verification in the presence of full-chip dynamic IR-drop. The degradation in the clock signal due to dynamic IR-drop is demonstrated on a small example as well as upon a large chip. In addition, we also discuss risks associated with assuming a static IR-drop budget upon clock propagation.