Multiple twisted data line techniques for coupling noise reduction in embedded DRAMs

New multiple twisted data line techniques to reduce both bit line (BL) and word line (WL) coupling noises in scaled embedded DRAMs are proposed and analyzed. An improved noise/signal ratio resulting from the application of the proposed techniques is confirmed by soft-error rate measurements on test chips with 256-Mbit and 1-Gbit level integration. At the 256-Mbit level, when the proposed techniques are applied to both the BL and WL structures, we achieved a 64% coupling noise reduction compared to the conventional twisted Bl (TBL) and WL schemes.