Digital demodulator implementation parameters evaluated by simulation

The performance of DSP receivers for digital communications is evaluated by computer simulation. The modulation is fast frequency shift keying. The confidence levels for the BER estimates are described and the parameters of interest are presented graphically. The effect of quantizer resolution, sample rate, signal level and synchronization timing error are quantified. The approach allows guidelines for the DSP designer who must otherwise implement a receiver within the constraints of a system design which typically compromises power consumption and component cost.