Dithered ADC systems in the presence of hysteresis errors

Dithering is a well-known technique employed in digital signal processing but generally it is assumed that the ADC to which dithering is applied has a uniform quantization step and no hysteresis errors. Several papers exist where the advantage of small and large scale dithering techniques are evaluated, concerning resolution improvements and total harmonic reduction of ADC digitizing systems. In the first part of this paper, an analysis of ADC hysteresis errors is made considering their effect on the quantization error and effective number of bits (ENOB) of an ADC system. In the second part of the paper a study of the improvements obtained using dithering in ADC systems with hysteresis errors is presented giving special attention to different time sequences of the dither signal.