A 1-Gb/s, 0.7-/spl mu/m CMOS optical receiver with full rail-to-rail output swing

This paper presents a 1-Gb/s optical receiver with full rail-to-rail output swing realized in a standard 0.7-/spl mu/m CMOS technology. The receiver consists of a 1-k/spl Omega/ transimpedance preamplifier followed by a postamplifier based on a biased inverter chain. The latter performs both a linear and a limiting amplification. The automatic biasing of the chain is provided through an offset tolerant replica circuit. The receiver requires no external components or biasing voltages. It is designed for a relatively large 0.8-pF input capacitance and is fed from a single 5-V power supply. These properties make the circuit suitable for a commercial environment. A sensitivity of 10 /spl mu/A was measured at 1 Gb/s. The complete receiver, including all biasing and replicas, consumes approximately 100 mW from the 5-V supply. When powered from a 3.3-V supply, a maximal bit rate of 600 Mb/s is achieved, while the power consumption is reduced to approximately 26.5 mW.