New experimental findings on process-induced hot-carrier degradation of deep-submicron N-MOSFETs

Severe hot-carrier degradation has been observed in deep-submicron N-MOSFETs, and is shown to be caused by several advanced device processing steps. These processing steps can also introduce significant changes in other device parameters, such as the threshold voltage and transconductance, etc., for devices without any hot-carrier stress. The two major achievements of this work are that: (1) we systematically illustrate that the process-induced lifetime degradation is most sensitive to details of back-end wafer processing, particularly when it involves high density plasma (HDP-CVD) oxide deposition and H/sub 2/ annealing; (2) we demonstrate experimentally, for the first time, that using a properly designed SiN pre-metal-dielectric (PMD) liner process can most effectively stop the back-end process-induced lifetime degradation. This result is different from previous reports which indicated that an additional SiN liner could further degrade the device lifetime (Tokitoh et al., 1995 and 1997; Cheek et al., 1997). We show that this apparent inconsistency is partly because one must be very careful in designing the liner process to make it work properly, and partly because the previous studies did not cover back-end process-induced hot-carrier effects.