Microprocessor reliability performance as a function of die location for a 0.25 /spl mu/, five layer metal CMOS logic process

In this paper, we present the results of multiple correlations between reliability (infant mortality and other reliability metrics) and yield on a die level basis for an advanced microprocessor fabricated using a 0.25 /spl mu/m, five layer metal CMOS logic process. Traceability information was programmed into each unit; infant mortality of edge die verses center die, effects of unusual sort yield signatures on infant mortality, alternating row effects, and the sources of variability of burn-in failures were investigated. The model with reliability defect density proportional to yield defect density was found to be in excellent agreement with experimental data over a wide range of yield values. The x-y die position yield was found to be an excellent predictor of infant mortality. The variation in infant mortality from wafer to wafer was found to be twice the lot to lot variation, consistent with the large number of single wafer processing tools used on advanced fabrication processes. As the traceability information is part of the standard manufacturing flow, this analysis was performed using a very large 1 million unit sample size. Die near the edge of the wafer were found to have worse reliability than those near the center; certain die locations were particularly poor. Unusual yield signatures at wafer sort often showed the same map of failures in burn-in. The level of resolution possible from a die level analysis also allowed us to identify specific tools and interactions between tools in the fabrication process which were responsible for reliability failures.