A 46 $\mu \text{W}$ 13 b 6.4 MS/s SAR ADC With Background Mismatch and Offset Calibration

A 6.4 MS/s 13 b ADC with a low-power background calibration for DAC mismatch and comparator offset errors is presented. Redundancy deals with DAC settling and facilitates calibration. A two-mode comparator and 0.3 fF capacitors reduce power and area. The background calibration can directly detect the sign of the dynamic comparator offset error and the DAC mismatch errors and correct both of them simultaneously in a stepwise feedback loop. The calibration achieves 20 dB spur reduction with little area and power overhead. The chip is implemented in 40 nm CMOS and consumes 46 μW from a 1 V supply, and achieves 64.1 dB SNDR and a FoM of 5.5 fJ/conversion-step at Nyquist.