A Fractional-N DPLL With Calibration-Free Multi-Phase Injection-Locked TDC and Adaptive Single-Tone Spur Cancellation Scheme

This paper proposes a fractional-N digital phase locked loop (DPLL) architecture with calibration-free multi-phase injection-locked time-to-digital converter (TDC) and gradient-based adaptive single-tone spur cancellation scheme. By using the injection-locked ring oscillator, the TDC quantization step is automatically tracked with the period of the digitally controlled oscillator (DCO) over PVT, and hence is free of calibration. The multi-phase TDC further achieves a fine resolution of 7 to 12 ps, depending on the DPLL's operating frequency. The proposed single-tone spur cancellation scheme achieves more than 40 dB spur suppression. The proof-of-concept DPLL prototype is implemented in 65 nm CMOS technology and synthesizes frequencies from 2.7 to 4.8 GHz with a 1V supply, consuming 21.2 mW. The measured in-band phase noise is -92 dBc/Hz at 40 kHz offset, the far out phase noise is -130 dBc/Hz at 3 MHz offset, with a reference spur of -86.5 dBc.