100-MHz serial access architecture for 4-Mb field memory

A 4-Mb field memory with a 100-MHz serial access rate has been developed. A new architecture that significantly improves serial I/O operation speed, reduces layout area, and offers simple control is proposed. To accomplish this task, a new architectural data shifter and high-speed redundancy circuit have been developed. The field memory has a 568-line*960 pixel*8-b (4,362,240 b) memory cell array designed for high-definition television (HDTV) screens. A 1.0 mu m CMOS process technology is used to produce a die size of 12.94 mm*25.9 mm. The write-read cycle time is 9 ns, the access time is 8 ns, and the active current is 170 mA at a 50-MHz cycle rate with a standby current of about 3 mA.<
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