Optimization of nMOS high-frequency transistor characteristics for application in MMICs

In this paper, we present the high-frequency (HF) performance of coplanar nMOS transistors with a gate length of 0.1 /spl mu/m. During device fabrication, several splits for the extension implantations have been chosen in order to investigate the DC and HF performance. In our experiment, it is shown that the DC characteristics of the devices with the lowest extension implantation dose give the best result in terms of the short-channel effect, while the HF performance shows the optimum for the highest implantation dose. This shows that the source/drain junction architecture plays a key role in both digital and analog applications.