Automatic verification of library-based IC designs

A new method is presented for fully automatic verification of layout, generated with a library-based IC design system. The method overcomes the limitation of traditional simulation-based verification techniques. It is based on a stepwise bottom-up reconstruction of large architecture building blocks, starting from the layout. Using a pattern matcher, the simplest cells in the transistor netlist, such as inverters, NAND gates, etc., are identified first. Then the pattern matcher is used again to find the next level of cells, such as memory cells, flip-flops, etc. Reconstruction of more and more complex structures takes place, until the architecture level is reached. To be able to communicate instances of parametrized library modules, the parameters have to define the module's connectivity in a unique way. For every module, a controller can then be established which guides the reconstruction process. When the design is correct, the reconstruction will succeed. On the other hand, if at some point the reconstruction fails, this indicates incorrect connectivity at that point.<
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