A general-purpose high-speed equalizer

The circuit presented is a high-speed self-adaptive filter achieving equalization over a wide range of signals, with a frequency of up to 40.5 MHz, as for the European D2-MAC and high-definition multiplexed analog components (HD-MAC) transmission standards. The circuit is a self-adaptive 16-tap transversal filter achieving equalization on any 8-b coded signal. It contains periodically a window of binary or duobinary data samples, such as the D, D2, and HD-MAC signals. This chip includes a delay line of 240 8-b data samples which are used for the internal gradient computations. Only linear distortions (echos) can be corrected by this chip. This 105000-transistor chip has been designed in a CMOS 1.0- mu m technology and is being used in a D2-MAC reception environment.<
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