Pushing the Limits of Bonded Multi-Wafer Stack Heights While Maintaining High Precision Alignment

The last decade in advanced microelectronics has shown great interest in 3-D architectures, which was paved by multi-wafer alignment technologies. However, many limitations remain in the fabrication of ultratall stacks as the alignment becomes more challenging and very costly. In this paper, a new cost-effective alignment technique was employed using a set of sapphire rods in through-wafer holes. Cross-sectional analysis, edge profilometry, and electron transmission tests showed ~2 μm alignment tolerances over 1 cm and ~4 μm over 10-cm tall stacks. An off-angle gold sputtering method was developed to fully coat vias of 5:1 aspect ratio before bonding. Also, a new “Stamping” technique is introduced to coat the vias to a desired height where necessary. In this paper, parallel microtubes with the aspect ratios of 1000:1 were formed by aligning ~200 wafers, each including 20000 gold-coated vias for storing charged particles.