A Hybrid Pad-Line-Finger De-Embedding Technique for Broadband Modeling of CMOS Transistor

A hybrid cascade series-parallel based de-embedding technique is presented in this letter for accurate broadband modeling of CMOS transistor. Specifically, it relies on a unique set of PAD-LINE test structures to extract line and pad parasitics without any inaccurate lumped assumptions. Additional FINGER OPEN-SHORT structures are used for further removal of interdigital finger parasitics. As compared to others, it is capable of accounting for metal finger parasitics and distributed effects of metal interconnections plus pad simultaneously. The proposed de-embedding technique has been validated on RF parameters of NMOS device for up to 100 GHz. It has been demonstrated to be more physical than conventional de-embedding approaches and previous work in removal of fixture parasitics for up to metal fingers.