A $3\times 60\;\text{Gb/s}$ Transmitter/Repeater Front-End With $4.3\;{\rm V}_{\rm PP}$ Single-Ended Output Swing in a 28nm UTBB FD-SOI Technology

A versatile three-lane transmitter/repeater array was designed and manufactured in a production 28nm ultra-thin body and BOX (UTBB) FD-SOI CMOS technology. Each lane in the array can operate at 60 Gb/s with adjustable output swing between 2.6 and 4.3 Vpp with a measured input sensitivity of 10 mVpp at 40 Gb/s, and requires at least 40mVpp input signal level to fully saturate the output driver for maximum swing operation at 60 Gb/s. Scaled, cascaded single-ended CMOS inverter transimpedance amplifiers with resistive and inductive feedback and interstage series inductive peaking were used to form the preamplifiers of each lane. These were optimized for maximum bandwidth and large gain, and drive the >4Vpp swing series-stacked cascoded CMOS inverter output stage. The single-ended CMOS-inverter topologies ensure that the total power consumption scales with the data rate and reduce the lane footprint to that of a ground-signal pad I/O. The measured lane-to-lane isolation is better than 40 dB up to 55 GHz, while the measured Tx-toRx dynamic range, defined as the ratio of the maximum output swing and corresponding minimum input voltage and sensitivity, is larger than 54 dB up to 40 Gb/s.