IC Substrate Package Yield Prediction Model and Layer Level Risk Assessment by Design Analysis

We present a method for quantifying a risk for killer defects at layer level and estimating yield for substrate packages using information from design files. To calculate risk ranks and predicted yield, we define a risk distance that is a key parameter extracted from designs using image processing techniques. In order to validate our model, we analyze two different designs, each having multiple layers, and compare with data from baseline lots. It is shown that there is an inverse correlation between risk layer ranks and yield. Estimated yield based on our model is compared with baseline yield for four layers of the second design. The model-to-baseline yield difference is less than 1% for three layers we tested.