Recent ASICs developments in 65nm CMOS technology for high energy physics experiments

The High Luminosity Large Hadron Collider (HL-LHC) will constitute a new frontier for the particle physics after the year 2024. The CERN experiments will undertake a major upgrade in order to stand this challenge: the use of innovative sensors and electronics will be have a main role on this. This paper describes the recent developments in 65nm CMOS technology for readout ASICS of future HEP experiments. These allow unprecedented performance in term of speed, low noise, low power consumption and highly granular tracking detectors.