Photon-Induced Negative Capacitance in Metal Oxide Semiconductor Structures

Design and fabrication of photon-induced negative capacitance is presented. The capacitor is implemented using Silicon on Insulator Metal Oxide Semiconductor platform, where the gate dielectric is made of a nonferroelectric material. Operating at room temperature, when the device is illuminated, in depletion mode the total capacitance grows in magnitude to values larger than the geometrical capacitance. We believe this is caused by the trap states existing at the interface of dielectric and semiconductor layers, and present the supporting modeling results. Using our model, we investigate the role of the trap density and light intensity, as well as the device geometry such as gate-ground position and the thickness of the silicon layer. Our model shows the depletion capacitance can grow to values more than three times larger than the geometrical capacitance.