A Low-Power ASIC Signal Processor for a Vestibular Prosthesis

A low-power ASIC signal processor for a vestibular prosthesis (VP) is reported. Fabricated with TI 0.35
$\mu$
m CMOS technology and designed to interface with implanted inertial sensors, the digitally assisted analog signal processor operates extensively in the CMOS subthreshold region. During its operation the ASIC encodes head motion signals captured by the inertial sensors as electrical pulses ultimately targeted for in-vivo stimulation of vestibular nerve fibers. To achieve this, the ASIC implements a coordinate system transformation to correct for misalignment between natural sensors and implanted inertial sensors. It also mimics the frequency response characteristics and frequency encoding mappings of angular and linear head motions observed at the peripheral sense organs, semicircular canals and otolith. Overall the design occupies an area of 6.22 mm
$^{{{2}}}$
and consumes 1.24 mW when supplied with
${\pm} 1.6$
V.