Effects of die location on hot-carrier response of plasma-etched NMOS devices

Plasma-process-induced charging voltage for a device may be positive (gate is positive with respect to the substrate) or negative depending on the location of the device on the wafer. The negative charging damage increases the number of trapped holes closer to Si-SiO/sub 2/ interface while the positive charging damage does not. This number of trapped holes also depends on the antenna ratio. The trapped holes closer to the Si-SiO/sub 2/ interface gets compensated by hot electrons injected during hot-carrier stressing. Thus, the type of charging voltage and the antenna size determines the hot-carrier response of a device. In addition, the differences in hot-carrier response for devices with varying antenna ratio are shown to be varying linearly with the differences in prestress subthreshold characteristics. This finding has the potential to reduce the hot-carrier stressing time or determine the most vulnerable devices without actually carrying out the experiments.