Accurate statistical process variation analysis for 0.25-/spl mu/m CMOS with advanced TCAD methodology

Effects of statistical process variation on the 0.25-/spl mu/m CMOS performance have been accurately characterized by using a new calibrated TCAD methodology. To conduct the variation analysis, a series of TCAD simulations was conducted on the basis of DoE (design of experiments) with optimum variable transformations, which resulted in RSF's (response surface functions) for threshold voltage (V/sub th/) and saturation drain current (I/sub ds/). A new global calibration of the RSF model based on experimental data gives excellent accuracy within 0.02 V error in V/sub th/ and 3% error in I/sub ds/. Using calibrated RSF, statistical process variation effects on the device characteristics have been quantitatively evaluated for each process recipe. It is found that variation of the gate-oxide formation process shows the most significant effect on the NMOS /spl Delta/I/sub ds/ in the production process. Furthermore we have designed an optimized 0.25-/spl mu/m CMOS process and device on the basis of the RSF and also predicted the process variation effects on the device performance. It is shown that the V/sub th/ and I/sub ds/ variations of the 0.25-/spl mu/m CMOS exhibit less than 10% I/sub ds/ variation in the production level process, which is similar to the value of 0.35-/spl mu/m CMOS experimental data. Additional TCAD simulations for MOS model parameter generation of the 0.25-/spl mu/m device was also conducted to allow circuit-designers to use predictive worst case circuit design parameters before experimental chip fabrication.