On short circuit power estimation of CMOS inverters

Traditional power optimization and estimation techniques for digital CMOS circuits have focused on the dynamic power dissipation, caused by charging and discharging the load capacitances at the gate outputs. However, as the device size and threshold voltage continue to decrease, the short circuit power dissipation is no longer a negligible factor. We show that previously published models for the short circuit power can not provide the accuracies required for current technologies. To improve the accuracy, we propose a new semi-empirical short circuit power model. Comparison of the proposed model with HSPICE simulation results on CMOS inverters using the Rockwell 0.25 /spl mu/m CMOS process parameters show that proposed model is significantly more accurate for estimating the short circuit power than the models reported in the literature.