Dynamic behaviors of an integrated circuit for recurrent neural networks

In order to investigate dynamic behaviors of recurrent neural networks or asymmetric interconnection networks on neuro-chips, we design a hardware neural network with programmable synaptic weights according to the design rule of a CMOS technology. The full connections between neurons and the self-coupling can be performed. Some types of connections can produce many limit cycles on the network. The number of limit cycles increases sharply with increasing the number of neurons in case of nearest neighbor connections. As an example, there are at least 1.14/spl times/10/sup 7/ limit cycles in the case of 40 neurons. The limit cycles have basins of attraction, and hence, we may utilize the network as associative memory to retrieve dynamical cyclic patterns. After the SPICE simulation for the network, we fabricate the integrated circuit. The chip size is 4 mm/spl times/4 mm or 2.2 mm/spl times/2.2 mm. The main part of the chip has 49 synapses and 98 SRAM cells each two of which belongs to each synapse to store its weight. We present a procedure to construct the synaptic weights to produce particular limit cycles in a network. The procedure to make up a connection matrix is useful for hardware implementation in terms of the simple synaptic weights and its accuracy.