A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS

A low power 14Gb/s transceiver using partially segmented voltage-mode driver, charge-based analog front-end, and low power clock and data recovery circuit that also minimizes clock distribution power is presented. Fabricated in a 65nm CMOS process, the transceiver achieves a power efficiency of 2.8mW/Gb/s and BER<10
⁻¹²
while operating at 14Gb/s with 12dB channel loss.