Architecting 3-D integrated circuit fabric with intrinsic thermal management features

Migration to 3-D provides a possible pathway for future Integrated Circuits (ICs) beyond 2-D CMOS, which is at the brink of its own fundamental limits. Partial attempts so far for 3-D integration using die to die and layer to layer stacking do not represent true progression, and suffer from their own challenges with lack of intrinsic thermal management being among the major ones. Our proposal for 3-D IC, Skybridge, is a truly fine-grained vertical nanowire based fabric that solves technology scaling challenges, and at the same time achieves orders of magnitude benefits over 2-D CMOS. Key to Skybridge's 3-D integration is the fabric centric mindset, where device, circuit, connectivity, thermal management and manufacturing issues are co-addressed in a 3-D compatible manner. In this paper we present architected fine-grained 3-D thermal management features that are intrinsic components of the fabric and part of circuit design; a key difference with respect to die-die and layer-layer stacking approaches where thermal management considerations are coarse-grained at system level. Our bottom-up evaluation methodology, with simulations at both device and circuit level, shows that in the best case Skybridge's thermal extraction features are very effective in thermal management, reducing temperature of a heated region by up to 92%.