A study on detailed placement for FPGAs

Recent Field Programmable Gate Arrays (FPGA) have high logic capacity and it requires fast yet high quality placement method for mapping a technology mapped netlist of a given complex digital design onto the FPGA chip. Analytical placement for FPGAs show significant scalability for large design compared to traditional simulated annealing based placement methods. However, the high quality placement achieved during global placement with overlap of logic blocks need to be legalized and fine-tuned during detailed placement efficiently in order to take advantage of the scalability of the analytical placer without compromising the quality. In this work, we study the effect of two different detailed placement methods, i) wirelength-driven, and ii) timing-driven on a legalized placement by proposing a suitable strategy specifically for FPGAs. The experimental results show significant improvements of the legalized placement in terms of half-perimeter wirelength and critical path delay, emphasizing the need for better detailed placement methodologies.