Power efficient implementation of bit-parallel unrolled CORDIC structures for FPGA platforms

Power consumption is one of the major concerns while mapping designs on FPGAs. Dynamic power dissipation in FPGAs is a strong function of the switching activity of the nodes and the charging and discharging capacitances associated with the critical path. This paper focuses on reducing the power dissipation in bit-parallel unfolded CORDIC structures by modeling the switching activity and the charging/discharging capacitances within the critical path. Two approaches have been used; the first one reduces the switching activity by hiding the high activity nodes within look up tables and the second one retimes the structure to reduce the critical path and the associated charging/discharging capacitances. A comparative analysis of our implementation results against the traditional approach has been carried out for varying input word-lengths ranging from 4 to 32-bit parallel operands. The implementation targets two different FPGA families viz. Spartan-6 and Virtex-5. The analysis concludes that a 10 to 20 percent reduction in dynamic power dissipation and 35 to 40 percent reduction in total power dissipation is achievable with these approaches.