Reduction of spatial data redundancy in implantable multi-channel neural recording microsystems

An approach is proposed for the reduction of redundant spatial information recorded by implantable high-density neural recording microsystems. This approach is based on a modified form of the whitening transformation, which is efficient enough (in hardware implementation) to comply with the hardware design constraints associated with implantable microsystems. Based on the proposed approach, a 32-channel processor is designed, prototyped, and tested for a large library of prerecorded multi-channel single-unit neural signals and synthesized signals. Designed in a 0.18-μm standard CMOS technology, the processor occupies 0.3 mm
²
of silicon area and consumes 238 μW @1.8V/1.28 MHz.